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你说的PIXCLK管脚属于并排的CMOS管脚：
MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
// MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN,
MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
MX6Q_PAD_GPIO_0__CCM_CLKO, /* camera clk */
MX6Q_PAD_SD1_DAT0__GPIO_1_16, /* camera PWDN */
// MX6Q_PAD_SD1_DAT1__GPIO_1_17, /* camera RESET */
那个管脚的频率的话，应该跟COMS驱动和管脚配置有关，详细有CPU控制
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发表于 2016-10-11 15:14:50
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发表于 2016-10-12 14:55:03
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