#define IPU_NUM 1 /* 1 for IPU1, 2 for IPU2. */
#define DI_NUM 1 /* 0 for DI0, 1 for DI1. */
#define LVDS_PORT 1 /* 0 for LVDS0, 1 for LVDS1. Note: LVDS and DI should be same number. */
#define DI_CLOCK_EXTERNAL_MODE /* When clock external mode was defined, the DI clock root will be PLL3 PFD1, without this macro, the DI root clock is IPU internal clock. */
/*#define LVDS_CLOCK_SRC_PLL5*/
#endif